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Capped vias are defined in Valor NPI documentation in several places.
The most complete definition of capped vias can be found in Valor NPI Assembly Analysis User Guide, under Padstack Analysis.
Valor NPI Assembly Analysis User Guide (siemens.com)
“Vias can be capped or uncapped, as determined by the boolean attribute
Capped Via. If the outer layer pad if a via has this attribute, the via is
considered capped on that side of the board. When referring to the drill
layer feature of the via, the via is considered capped when either of its
outer layer pads has the Capped Via attribute..”
Also, most analysis categories that report capped vias in various contexts include a definition of capped.
In Valor NPI Fabrication Analysis User Guide, you will note that there is a control put on this definition (for fab analysis) by the erf variable v_exposure_by_is_capped:
Valor NPI Fabrication Analysis User Guide (siemens.com)
v_exposure_by_is_capped - Controls how a via is considered exposed.
no — A via is considered exposed if not covered in
the solder mask layer. (default)
yes — A via is considered covered if assigned
attribute Capped Via, even if exposed in the solder
mask layer.
If you are using MRA-R for Fabrication Analysis, this modifier can be found in the ACM under the name “Signal – Report capped vias”
If Valor NPI System Management User Guide, you will also find the following definition (using the internal attribute name .is_capped):
Valor NPI System Management User Guide (siemens.com)