Hyperscaler computing pushes design requirements to the extreme, including component and routing density, signal speed, power utilization and thermal dissipation. For the systems designer, these large, complex designs operate with extraordinarily small timing and voltage margins, which means that modeling and simulation work has to be highly accurate to ensure that the design will work in production. While accurate modeling of critical structures with full-wave electromagnetic solvers is essential, it’s also critically important that design simulations represent the board as will actually be manufactured, instead of just the way the system designer wants it to be fabricated.
In this webinar, we’ll discuss the process of exploring design options, optimizing critical structures and verifying system-level operating margins for a system using a combination of 56 and 112G optical links. We’ll show how the behavior of all the serial links can be accurately modeled and verified for the design as it will be manufactured, thereby maximizing the chance for first-pass design success.
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Q&A
Q: Is automation required? Am I even ever able to run this process manually?
A: Yes, you can run this process manually as shown in the first part of the demo. The selection of nets, creation of 3D areas, solving, and SerDes compliance can all be done within the HyperLynx GUIs. Automation is not required; however, automation does provide some major benefits. Mainly that the consistency and reliability of the process is much better. Rather than manually setting up the design and simulating iteratively, scripts can automate this process and ensure that the design is setup exactly the same way every time.
Q: My designs are nowhere near this big. Can I still use HyperLynx to verify a smaller design? Can I do this process for 10 nets?
A: Yes, this system-level verification is not limited to only large designs. HyperLynx is capable of analyzing all designs, from small boards all the way to massive designs found in Hyperscaler computing applications and aerospace electronics. HyperLynx does particularly excel at verifying large designs since we are able to model and simulate all nets on the post layout design including any critical areas modeled in 3D with the full wave solvers.
Q: How long would the calculation work on my board? I have 50 channels that I want to solve. How many 3d areas would that be? How long would it take on a single machine?
A: There’s no definitive answer to this exact case. The number of areas and total solve time would depend on the topology of the channels and how many layer transitions are present. In terms of total solve time, the layer count of the board as well as the size of the 3D area models to be solve will affect the overall compute time required. The sequential solve time on a single machine for 94 areas on the SDK180 design which is a 28-layer stackup would have taken upwards of 50 hours but we were able to accelerate this solve time with JD and complete the solves in under 5 hours.
Q: What protocols are available? Do you support PCIe Gen5 protocol?
A: Yes, PCIe Gen5 is supported. HyperLynx also supports upwards of 200 other protocols with more being added every release.
Q: Once I optimize the via on one net, can I just apply that result to all of my vias?
A: The optimized via structure will be valid for all nets with the same via layer transition. So, for example the via we optimized transitioned from the top layer to inner layer 26 so we could use these optimized parameters for all other nets that use the same via transition. But for other nets that have different layer transitions we would need to complete another via optimization.
Q: How do you demo this?
A: Talk to your local Siemens representative for more details on this SDK180 database and using HyperLynx for full-system level verification and design space exploration on your own designs. Contact Us
Q: How does the tool determine what areas require the 3D solver?
A: HyperLynx determines which areas require 3D electromagnetic modeling by finding portions of net where TEM current flow is disrupted.
Q: Is HL-DSE different than the HLAS 3D Explorer?
A: Yes, HLAS 3D is different from HLDSE; however, they interface and work together. When you use HyperLynx Full-Wave Solver or another Advanced Solvers tool, you set up a simulation to represent a design that you want to evaluate. If you want to evaluate the effect of a different or varying design property (such as trace width), you copy a simulation, edit its Layout, run a solver, and compare results from the original simulation to results from the copied simulation. 3D Explorer automates much of this work by: gathering design variation information from you, creating a project that includes a simulation for each design variation, running a solver on each simulation, and consolidating results for all simulations into a report.
3D Explorer projects can be exported to HLDSE where they can be used as the source project for an optimization study. Variables and responses from the project can be tagged for variability and measurement. HLDSE then automates the process of varying the design variables, simulating the design iteration and then measuring the responses. The SHERPA algorithm used by HLDSE, employs multiple search strategies at once and adapts to the problem as it learns about the design space.
Q: Could you provide us with the Python code to automate the post-layout simulation in HyperLynx? Additionally, are there any insights or guidelines on implementing this automation? If possible, could you share any relevant documentation or best practices?
A: Yes, the Python scripts shown in the demonstration are available to be used and customized to your workflow and design process. Please contact your local Siemens AE (Contact Us) for more details on Python Scripting and obtaining access to these scripts used. HyperLynx scripting documentation is also available in the install directory as well as on Siemens Support Center: HyperLynx SI/PI Scripting - Tips and Tricks, HyperLynx DRC Automation Wizard, HyperLynx Advanced Solvers Scripting Guide, Task Automation Using Scripts in SI/PI
Q: What the optimization algorithm used in the HL-DSE?
A: HL-DSE uses a hybrid and adaptive algorithm called SHERPA as its default search method. SHERPA employs multiple search strategies at once and adapts to the problem as it learns about the design space. To identify optimized designs, SHERPA requires significantly fewer model evaluations than other leading methods and SHERPA often finds a solution the first time. During common engineering optimization studies, this efficiency save days or even weeks of CPU time.
Q: Does HyperLynx have a full 3D solver or is this handled by another product?
A: Yes, HyperLynx Advanced Solvers suite has the Fast3D solver, Hybrid Solver, and a Full-Wave Solver. Full-Wave Solver was used in this demonstration to solve the 3D areas and optimize the via structure.
Q: Can this approach be used used with HDI designs, that consist of micro vias that step down through the outer layers and connect from top to bottom with Core vias (Buried vias)
A: Yes, this approach can be used with HDI designs and HyperLynx supports stacked vias (micro via on top of a buried via).
Q: What license options are required for the tools seen today as compared to the existing Advanced Solvers, and are additional seats needed when doing parallel computing?
A: The tools shown in the demo include HyperLynx SI/PI, HyperLynx Full Wave Solver, HyperLynx 3D Explorer, and HyperLynx DSE. Licenses would be required for those tools in order to complete the full workflow. In regards to 3D area solving, existing Full-Wave Solver licenses are sufficient for solving 3D areas. When running many jobs in parallel, additional Full-Wave Solver licenses would be required that match the number of desired parallel jobs.
Q: I noticed you are analyzing the nets at the source of the signal. shouldn't we be more concerned about the signal at the load or receive end?
A: Great point. As opposed to backplane or chip-to-chip topologies, where most of the requirements are defined end-to-end (from transmitter to receiver or vice versa) the VSR/C2M interfaces have more complex specifications that include: Host Compliance Board (HCB) and Module Compliance Board (MCB) test methods for host/module input/output compliance.
Q: I have the software but not much docs comparing to Ansys SI! Do you have examples that we can explore ?
A: Yes, there are examples to explore. HyperLynx On Demand Training as well as HyperLynx Workshops are great resources to get started with. KB000156563_EN_US available on Siemens Support Center has more details on accessing HyperLynx ODT and Workshops in the cloud.