Calibre Deep Dive Into 3D PERC Analysis: Running PERC for 3D IC Design with 3DSTACK (Episode 3)

Q&A  
 
Note: 
1. Thank you all for the questions during the webinar! Below is the transcript of the questions and answers.
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Q) How does 3DPERC check work for dies that are from different technologies? 
A) Each die is initially analyzed standalone with Calibre PERC using the specific foundry PERC PDK corresponding to its technology node. One of the primary inputs for 3DPERC checks is the "dfmdb", generated for each die during this individual analysis.

Q) Which foundries PDK complies with Calibre 3D stack methodology? Is STM included in this methodology?
A) TSMC provides 3DSTACK decks, but designers must specifically request a 3DSTACK deck from the foundry.

Q) Are fabs typically setting reliability constraints covering both die-interposer and even up to package that 3Dperc can check against?                               
A) Fabs are actively working on setting such reliability constraints. Calibre 3DPERC supports constraint switches, which fabs can use to define these parameters for comprehensive 3D verification checks. 

Q) For running 3dPERC, should the design need to be 3DSTACK violation CLEAN (i.e. fullConnect_assembly, Centers, Overlap checks etc ... )                             
A) It is recommended that the design be free of 3DSTACK violations, particularly in terms of overlap and connectivity. Similar to 2D designs, connectivity issues such as shorts/opens can impact ESD analysis.

Q) What are the licenses required for 3D PERC?                                                       
A) To perform 3D-aware die analysis, the following licenses are needed:

          Calibre PERC Ap SW                       « part number: 293030, feature name: calibreperc »

          Calibre 3DPERC (die2die) Op SW   « part number: 298275, feature name: calibrepercd2d »

To perform 3DIC analysis, the following licenses are needed:

          Calibre PERC Ap SW                              « part number: 293030, feature name: calibreperc »

          Calibre 3DPERC (die2die) Op SW          « part number: 298275, feature name: calibrepercd2d »

          Calibre 3DSTACK Advanced                  « part number: 298753, feature name: cal3dstackadv »

Q) 3DSTACk PERC P2P  - has 2 values min, Max ( perc::get_effective_resistance command)  
A) perc::get_effective_resistance is not used for PERC-LDL P2P analysis. This command is used in topology analysis on intentional devices not interconnect parasitics.

Q) When is a 3dstackadv license needed?                                           
A) This license is needed for the new advanced flows:

         3DPERC
         Inter-chiplet Antenna checking
         Inter-chiplet DRC

The traditional connectivity and alignment checking does not require this license. They require only DRC/DRC-H, LVS/LVS-H & DRV.

Q) What challenges might arise in terms of thermal effects when working with 3D IC designs in Calibre 3DSTACK, and how can they be mitigated?
A) In 3D IC designs, thermal dissipation is a critical issue due to the stacking of multiple dies, which can surely create hotspots. The best solution might be the correct packaging that will reduce thermal effects. Additionally, using tools like 3DThermal helps model the impact of heat and suggests modifications to mitigate thermal issues.

Q) How does the use of Calibre 3DSTACK in combination with 3D PERC enhance reliability in advanced 3D IC designs?
A) By using Calibre 3DSTACK alongside Calibre PERC, designers can perform more thorough reliability checks. The PERC analysis allows designers to apply custom checks and constraints on specific paths or regions within the 3D IC, particularly for power, electrical integrity, and thermal issues. Combining the two enables a more detailed and reliable verification of 3D structures, reducing the risk of failures in complex designs.

Q) What specific challenges arise in 3D ICs when performing PERC analysis across multiple dies?
A) In 2.5D ICs, dies are placed side-by-side on a silicon interposer, and in 3D ICs, the dies are stacked on top of each other. The need to manage interconnect reliability and current flow between these dies becomes critical. This brings us to challenges like differentiating between external and internal I/O, handling CDM (Charged Device Model) and HBM (Human Body Model) constraints, technology node differences, etc.