Calibre Integrating 3DSTACK with PEX: Essential Data and Workflow for Parasitic Extraction (Episode 2)

Q&A  
 
Note: 
1. Thank you all for the questions during the webinar! Below is the transcript of the questions and answers.
2. If more support is needed for any of the issues you are facing, please open a support case at  https://support.sw.siemens.com/en-US/support-case/open 

Q) What is the primary focus of the "Calibre 3DSTACK – PEX Files Generation" process?
A) This utility focuses on generating parasitic extraction (PEX) files to capture parasitic effects such as capacitance and resistance in 3D integrated circuits using Siemens' Calibre 3DSTACK tools.

Q) What are the main advantages of using 3D integrated circuits? 
A) 3D ICs offer better performance, higher interconnect density, and close proximity between components. They also enable smaller packaging with more I/Os and reduced insertion loss. 

Q) What do the terms "F2F" and "F2B" stand for in 3D IC packaging? 
A) These are basic 2-tier die bonding styles. "F2F" refers to Face-to-Face bonding of dies, while "F2B" stands for Face-to-Back bonding. Both methods are used in 3D IC stacking to enhance connectivity and performance 

Q) How does Calibre 3DSTACK interact with the Calibre PEX tool for parasitic extraction? 
A) Calibre 3DSTACK works with Calibre PEX by generating the interface annotated GDS and interface MIPT map files to extract die-to-die coupling capacitance and other parasitic effects. 

Q) What is the difference between the Semi-Automated Flow and Fully Automated Flow in 3DSTACK PEX generation? A) The Semi-Automated Flow requires manual generation of interface files and MIPT map files, while the Fully Automated Flow generates all necessary files for xACT automatically. In a Fully automated flow, the calibration process is running under the hood while in a semi-automated flow, the user needs to execute the calibration process manually. 

Q) Why is extracting die-to-die coupling capacitance important?
A) Die-to-die coupling capacitance significantly impacts the performance and accuracy of multi-die systems, especially in complex 3D stacks where interactions between dies must be accounted for. Ignoring the die-to-die caps can negatively impact overall performance. 
 
Q) What challenges are associated with parasitic extraction in 3D ICs?
A) Challenges include extracting parasitics from TSV (Through-Silicon Via) couplings, die-to-die interactions, and accurately modeling interactions between RDL (Redistribution Layer) and other elements.

Q) What are the key features of the Calibre PEX solution for 3D ICs? 
A) The Calibre PEX solution offers a comprehensive approach to parasitic extraction for 3D ICs. It can extract parasitics for both dies and interposers in a single run, covering front-end, middle-of-line, and back-end-of-line interconnects. The solution accurately models complex interactions, such as TSV-to-TSV couplings and inter-die interfaces like Face-to-Face (F2F) and Face-to-Back (F2B) bonding. Additionally, it accounts for local interconnect resistance and mask misalignment in multi-patterning, ensuring precise extraction at advanced nodes.

Q) What is the significance of TSV-to-TSV couplings in 3D IC designs? 
A) TSV-to-TSV couplings are critical for maintaining signal integrity and can significantly impact the overall electrical performance in 3D ICs, particularly in dense interposer designs. These couplings introduce parasitic capacitances and resistances between adjacent TSVs, which can lead to signal delay, noise, and power consumption issues. As a result, TSV coupling plays a major role in timing performance, and minimizing these effects is essential for optimizing the speed and reliability of the design. 
 
Q) How does Calibre 3DSTACK handle third-party parasitic extraction tools? 
A) Calibre 3DSTACK generates specific PEX input files, such as annotated GDS, MIPT files, and RC rules, which are specifically designed for Siemens' parasitic extraction tools like Calibre xACT. These files are encrypted and can only be processed by Siemens' tools, ensuring a secure and optimized workflow for parasitic extraction.  
 
Q) What is the purpose of the annotated GDS in 3DSTACK PEX?
A) The annotated GDS in 3DSTACK PEX (or, in general, PEX) serves as a key file that provides detailed information about the layout, including specific annotations for parasitic extraction. While the original GDS contains the basic design data, the annotated GDS includes additional derived layers specifically for capturing parasitic effects such as capacitance and resistance. To generate the annotated GDS, the Calibre Connectivity Interface (CCI) option must be enabled during the run 
  
Q) What challenges can arise from increased parasitic effects in large die stacks with interposers? 
A) Calibre PEX can extract parasitics for both dies and interposers in a single run, including the calculation of interposer TSV-to-TSV couplings. This combined extraction reduces the risk of underestimating parasitic effects by incorporating all the relevant interactions between the dies, interposer, and metal layers. Ensure both front and back side metal layers are included in the extraction for more accurate results. 

Q) How can inconsistent layer definitions in the MIPT file affect parasitic extraction?
A) Ensure that the MIPT map file and RC rules are thoroughly validated before starting extraction. The MIPT file should clearly define which layers are involved in die-to-die and interposer couplings. Calibre 3DSTACK helps generate consistent map files by integrating the assembly description with the Connectivity Interface (CCI) to model all layers accurately. 
 
Q) How can high parasitic coupling in dense TSV arrays affect signal integrity?
A) TSV-to-TSV couplings must be accurately modeled, especially in high-density designs. Calibre PEX calculates and inserts TSV coupling effects into the parasitic netlist based on predefined tables and accurate modeling of distance and frequency dependence. Ensure that S-parameters are used to capture frequency-dependent effects and rely on layout-dependent parametrization to control layout-related issues.  
Q) If two dies are the same will a coupling cap be present between them? 
A) When two dies are the same, the presence of a coupling capacitance between them depends on several factors, such as their physical placement in the 3D IC structure and how they are connected. 
In general, coupling capacitance can still exist between two identical dies if electrical signals or metal layers are close to them. This capacitance arises due to the electric fields interacting between the conducting layers or interconnects.
 
Q) Who does write the "rules" for parasitic extraction of the interposer, is there an example case to write my own?
A) The files are automatically generated during the flow. You can use EXPORT LAYOUT command in combination with a specific keyword to generate the RC rule file.
Currently, we don’t have an example case that we can share for testing purposes, but you can access a trial version and the virtual lab for 3DSTACK with the following link: Calibre 3DSTACK trial | Siemens Digital Industries Software