Calibre Calibre 3DSTACK: From 3D IC Basics to Advanced DRC and LVS Features (Episode 1)

Q&A  
 
Note: 
1. Thank you all for the questions during the webinar! Below is the transcript of the questions and answers.
2. If more support is needed for any of the issues you are facing, please open a support case at  https://support.sw.siemens.com/en-US/support-case/open

Q) Is Calibre 3DSTACK based on the layer stack or is it based on the technology data when there are multiple technology die stacked?
A) Calibre 3DSTACK is based on the layer stack, not on the technology data. From a 3DSTACK perspective, the underlying technology of the dies does not matter.

Q) Can a spacing check be implemented between die layers if the dies are from different processes?
A) Yes, spacing checks can be implemented regardless of the process. The technology used does not impact the spacing check.

Q) Will the Calibre 3DSTACK be capable of handling a die that is more than the reticle size directly or any additional method to follow?
A) We don’t understand this question completely, so it’s hard to give an accurate answer. If you need any assistance with it, please feel free to submit the case to the Support Center and share more details so we can provide you with an accurate answer.

Q) Will Calibre 3DSTACK be capable of handling both Passive Interposer and Active Interposer-based stacking?
A) Yes, Calibre 3DSTACK can handle both passive and active interposer-based stacking.

Q) For regular LVS checking, we OPEN RESISTOR network then checks SHORTS/ OPENS so the SHORTS/ OPENS are not due to resistor network. In 3D LVS as well do you think RESISTOR connection needs to be OPENED up? Or should we shorten via RESISTOR network then check SHORTS/ OPENS (between die)?
A) We need more details to provide you with an accurate answer. Could you please submit a case so that we can help you with this question?

Q) Is it possible to connect more than 2 dies?
A) Yes, connecting more than two dies is possible. There are multiple options for doing that and the selection of the method depends on your design requirements.

Q) Is the technology node for more than 2 dies connection developed yet?
A) Yes, the technology of more than 2 die connections has already been developed.

Q) Can the LVS be checked with full extraction of both dies?
A) You can check the connectivity in the assembly and the external connectivity between dies. However, by using the white box mode (by specifying the wb_connect option), you can check internal connectivity by defining the connectivity of layers inside the die.

Q) For Calibre 3DSTACK is there any max limit to the number of die or any max limit to the die size?
A) There is no inherent limit to the number of dies in Calibre 3DSTACK. Any limitation would depend on the computational resources available.

Q) For each interface net (die to die), do you believe there is also a need to include FULL LAYER STACK (M0, M1 ... till BUMP layer) using the routing layer instead of just using BUMP layer connectivity?
A) This depends on the specific case. In some cases, the full layer stack is required, while in others, only the bump layer is sufficient.

Q) Is tiling involved in 3DSTACK?
Yes, tiling is involved in 3DSTACK. We have a functionality for it, and if you need assistance with it, we can help with the implementation.

Q) Is it possible to follow 3DBlox-based implementation with Calibre?
Yes, Calibre 3DSTACK supports 3DBlox. You can source the 3DBlox file in the 3DSTACK rule file and run the flow.

Q) For extraction of inFO or POP packages or interposers what kind of rule files will be required?
A) We use the same set of input files, including the rule file, layout, and source netlist.

Q) 3DSTACK Demo: Will it be possible to get access to the DEMO test case that you have shared, so that we can try the DEMO test case?
A) Yes, you can access a trial version and the virtual lab for 3DSTACK through the following link:

https://trials.sw.siemens.com/high-density-advanced-packaging-trials/ 

For any further assistance, feel free to create a support ticket and contact our support team representatives.

Q) Can we have the lab to test it out?
A) The same answer as for question 14.

Q) Is there a limit to a number of dies that can be put in 2.5D? Is there a limit to a number of dies that can be stacked over one another in 3D?
A) There is no specific limit to the number of dies in either 2.5D or 3D designs from the 3DSTACK perspective.

Q) Earlier I've used Calibre -3d for interposer verifications. How is calibre -3dstack different from the calibre -3d. Do you have a new features document that outlines all the important features that I should be aware of?
A) The Calibre -3d option refers to Calibre xACT 3D, used in digital flows for LEF/DEF designs. Calibre 3DSTACK has a specific syntax used for executing 3DSTACK operations. We can provide documentation outlining the key differences and new features.

Q) Why do we need a 'tier' definition for 2.5D but not for 3D designs? Shouldn't this be the other way around?
A) Tier argument helps to specify existing dies and stacks placed at the same z-coordinate, allowing elements to be placed side-by-side. In 2.5D design dies are placed in the same z coordinates side by side, while in 3D design they are placed on top of each other and we don’t need to specify tier argument.

Q) Following up on 'tier' questions, then why do we have 'tier' for PoP designs given the dies are stacked?
A) The 'tier' definition is needed because die 1 and die 2 are not identical and are not positioned directly on top of each other. Specifying the tier option ensures that the tool places them on the same z-coordinate.

Q) How would you generate a combined LVS with Die, Interposer, and Package together? Would PKG CSV file accepted for Interposer to PKG connections?
A) To generate a combined LVS netlist we require the top-level netlist. Connectivity is extracted from the assembly (die, interposer, package) and compared with the provided CSV netlist.

Q) During die definition - layer name and type should be defined based on the ubump layer number and type? Please give more details on this layer definition for the die definition.
A) The layer name and type specified in the rule file don’t need to match to what is present in the GDS file. However, the layer number must be consistent with the layout.

Q) Are stack names hard-coded? Example 2.5D can only be recognized by assembly1.
A) Yes, stack names are hardcoded in the stack definition. Multiple stacks can exist, but each stack name must be unique.