Calibre Calibre PEX Series - Episode 3: Mastering Hierarchical LVS for Accurate Gate-Level Parasitic Extraction
Summary
In this Calibre webinar, we will show you how to master gate-level extraction setup and understand more about the interplay between your LVS setup and the hierarchical database provided to the PEX engines for a successful gate-level extraction run.
Details
Q&A
Note:
1. Thank you all for the questions during the webinar! Below is the transcript of the questions and answers.
2. If more support is needed for any of the issues you are facing, please open a support case at https://support.sw.siemens.com/en-US/support-case/open
Q: Are there any specific differences in the settings between the GUI and batch mode when running gate-level extraction using xcells?
A: There are no specific differences between the GUI and batch modes. Eventually, they both use the same invocation. In Batch mode, you need to use the -xcell switch and specify the xcell file. In the GUI, you need to choose gate-level extraction as your extraction type in the outputs tab, which will subsequently prompt you to specify the xcell file in the inputs tab.
Q: It will be very helpful to have more information about the differences between hcell and xcells. Are there any available?
A: Hcells stand for hierarchically corresponding cells. These cells should exist in both the layout and source and should (presumably) perform the same function.Calibre nmLVS-H uses the hcell list to define cell correspondence between layout and source.
During LVS extraction, Hcells are generally preserved and netlisted, however, they can sometimes be subjected to expansion depending on your LVS setting. Hcells are used later on during the comparison phase to do hierarchical LVS comparison between these cells in both layout and source, otherwise, If you do not specify hcells, the LVS-H circuit comparison to run flat.
XCELLS on the other hand are used only during parasitic extraction to specify a hierarchical extraction cell. When you specify an xcell list that is correctly identified, you can either run gate-level extraction for device blocking within specific cells (-xcell) or hierarchical extraction (-full -xcell) which is usually very useful for memory arrays since it shortens the extraction time and netlist size
Xcells should be preserved during LVS extraction since the downstream tools uses the hierarchy database passed on by the LVS during circuit extraction.
Q: How does the deprecation of certain BOX flows, like the GRAY BOX starting in 2023.3, impact current and future designs?
A: The most important thing for cell-based blocking is to maintain the hierarchy of cells during the LVS extraction. Usually specifying them as HCELL alone, will work. However, in case you are facing any issues with seed promotions, you should opt for the different preserve options during your run. The documentation also has reference to different options that you can use as a replacement for GRAY BOX flow.
Please refer to this section in the documentation:
Q: How does in-context coupling analysis enhance the accuracy of gate-level extraction for complex designs?
A: In-context coupling analysis helps by considering the in-context couplings around blocked xcells ensuring more accurate parasitic extraction. This approach captures the interactions between the xcell and its surrounding circuitry, leading to more precise simulation and modeling of complex designs.
Q: How do the Calibre decks facilitate the device blocking process for foundry devices versus custom devices?
A: If the foundry is using the device blocking per cell approach, you should make sure to specify the xcell list during your gate-level extraction run to avoid parasitic double-counting during your post layout simulation. Again, don’t forget to specify them as hcell accordingly in your LVS/PHDB step.
Q: What are the consequences of double-counting parasitics in pre-characterized cells during post-layout simulation?
A: Double-counting parasitics can lead to inaccurate simulation results, with overestimated parasitic effects causing incorrect performance predictions and potential design failures.
Q: What is the difference between gate-level extraction, and the other hierarchical run options?
A: They both need an xcell file in order to determine the hierarchical extraction cell.
In gate-level extraction(-xcell), Calibre PEX extracts nets down to top level xcells whereas the cells internal contents are blocked during parasitic extraction.
Hierarchical extraction (-full -xcell) on the other hand, extracts parasitics from within the xcell list, however if you have multiple cell instances of the same cell repeated multiple times in your design such as memory arrays, Each cell is extracted only once, which shortens extraction time and netlist size.
Q: Can you give examples of devices for which you would *not* want to use xcell? Because the spice model for a momcap will always include the internal capacicance, right?
A: All foundry provided pcells that are defined as xcells should be blocked through gate-level extraction. Anything outside foundry pcells are custom devices.
Q: What is the difference between transistor-level and gate-level extraction?
A: During transistor level extraction, all cells are flattened and the extraction is performed down to the primitive devices level.
In gate-level extraction, Calibre PEX extracts nets down to top level xcells whereas the cells internal contents are blocked during parasitic extraction. If your xcells are specified in an xcell file, use the -xcell switch with your xcell file. If your PDK is set in such a way that xcells are definied in your rules file through PEX XCELL SVRF statements, you will not need the -xcell switch. Calibre Extraction will extract nets down to top level xcells defined in your rules file.
Q: Can you also show how you have provided data in hcell and xcell files?
A: Please check out the following sections in the documentation
Q: In comparison results is the comparison done between transistor level and gate level extracted spf?
A: If you are talking about the demo that was demonstrated during the Webinar, then the answer is yes.
Q: What does PCDEF stands for?
A: PCDEF is an option that is used when a cell is specified as a pcell. The pcell contents are not extracted, however in-context couplings are still captured. The parasitics outside the pcell boundary will be extracted. For nets that exit an xcell through an xcell pin, the coupling capacitance between nets outside the xcell and nets inside the xcell will be extracted and netlisted connecting between the outside net and the xcell participating in the relationship. For nets totally enclosed within the xcell (they do not exit the xcell through any xcell pin), coupling capacitance is computed to the outside nets and is netlisted on the outside net dropped to ground
Q: Is it expected that the foundry PDK provide the xcell file? The end user would only need to modify it for custom devices.
A: Yes. If the foundry specifes its xcells using an external xcell file, then the foundry should provide that file, and the user should use gate level extraction by using -xcell invocation option with the provided xcell file. There are other foundries however, that define their xcells directly in their rule decks through a PEX XCELL statement. In this case, there is no external xcell file and you will not need the -xcell switch. Calibre Extraction will extract nets down to top level xcells defined in your rules file.
If you have custom devices, then add them to the already provided xcell file or put together a new file with the custom devices in case the xcell definitions are defined in the rule decks
Q: How do we handle a cell in which certain coupling capacitances are part of the post-layout model but certain other capacitances are required to be extracted by the pex tool?
A: In this case, layer based ignores using the appropriate PEX IGNORE CAPACITANCE DEVICE and PEX IGNORE RESISTANCE DEVICE statements should be the go-to option.
Q: In custom cells we may have multiple derived layers in the device in which we may have to selectively extract coupling caps, but NOT extract other couplings because the customer SPICE model does account for those coupling cap combinations.
A: In this case, layer based ignores using the appropriate PEX IGNORE CAPACITANCE DEVICE and PEX IGNORE RESISTANCE DEVICE statements should be thego-to option.
Q: Where in the PEX form do I specify PCDEF mode?
A: The PCDEF mode is an option that is defined per xcell definition. You can either use the -PCDEF switch in your xcell file or if you are using PEX XCELL SVRF statement to define your pcells, then you can use the optional PCDEF argument.
Please Refer to the following sections in the documentation:
Additional Resources:
How to make Calibre PEX block the extraction of parasitics for specified cells?
Want to extract only the parasitics between the hcells, but not the internal geometry?
https://support.sw.siemens.com/en-US/product/852852053/knowledge-base/MG65388
How to Extract In-Context Couplings for Pre-Characterized Cells In Calibre xRC?