With the increasing complexity of designs and stringent requirements, integrating and verifying hardware and software early in the design cycle is crucial for achieving optimal functionality, timing, and power performance. In this webinar, you will learn how ESL's higher abstraction models significantly enhance simulation performance compared to RTL simulation, enabling you to: • Perform architectural exploration to fine-tune and optimize your platform's performance. • Accelerate early software development and seamless integration with your hardware platform. • Support your hardware verification flow efficiently. Explore the practical applications of ESL through its supported standards and flows, including SystemC language, Transaction Level Modeling, Verification libraries, Virtual Platforms, and ESL's link to RTL with Universal Verification Methodology (UVM).
| Attachments: | Questa_SystemC_TLM2_lt_dmi_example_Visualizer_run_script.tgz (1 KB) Questa_SystemC_sc_vlog_example_Visualizer_run_script.tar.gz (869 bytes) scv_overview.tar.gz (4 KB) |
Q1: What is the supported SystemC version?
Questa/Visualizer 2024.x versions support SystemC 2.3.4 version (it should be compatible with previous versions)
Q2: What are the supported gcc versions for compilation and linking?
Note that on Linux it is part of Questa/Visualizer installation. On Windows you’ll need to download and extract it separately (it appears on Support Center site Questa/Visualizer download page)
Q3: And for SystemC debugging what is being used?
Questa/Visualizer runs on the background during simulation the GNU gdb 10.2 debugger version – so you can use in the commands prompt all its available and supported commands. Also when you set breakpoint for example – it will run the relevant gdb command and you’ll see its messages in the transcript window pane.
Q4: Can we use our own gcc installation?
In general you can do it and then you’ll need to point for it using the -cppinstall option of sccom command. However, you’ll need to be careful that the gcc version you use is compatible with the versions provided within Questa installation. Otherwise, you might face compilation or linking errors or unexpected behavior during simulation.
Q5: For mixed SystemC/HDL designs simulation is it only limited for top SystemC and lower level of Verilog as shown in the example during the presentation (using scgenmod command flow)?
No, you can have also Verilog instead of VHDL and also it can be with the opposite hierarchy – top Verilog or VHDL and lower level SystemC, and also more complicated hierarchies such as HDL on top then instantiation of SystemC and then another loser level instantiation of HDL. So, all options are supported.
Q6: What about SCV – SystemC verification library – as it is external library, is it needed to be installed separately?
No, it is part of Questa installation. You just need to use it in your SystemC code and use the -scv option for sccom compilation and linking commands.
Q7: Where the SystemC LRM can be found?
It can be downloaded from IEEE site and there are links to this location from systemc.org site
Q8:What is TLM1 and how it is related to TLM2 standard?
TLM1 was the first version of the Transaction Level Modeling standard – it includes some channels protocols such as fifo and mutex with blocking and non-blocking methods for data transfers. It was limited and reduced standard relatively to TLM2 which included much more utilities such as different socket types, payload structure for the transaction’s information, coding styles and much more. To keep compatibility, TLM1 was included in TLM2 standard class’s structure so it still can be used.
Q9: What is the source of the examples included in this presentation?
Note: All the above examples run scripts were modified to be suitable for interactive live simulation and debugging using Questa/Visualizer - please see in the attachments above the modified scripts for the TLM2 and sc_vlog examples.
Q10: It was mentioned that ESL can reduce time to market – what is the reason for that?
With ESL you can start the SW integration and its debugging and optimization within the full HW platform – and not wait for first HW platform physical prototype – that is what is known as “shift-left” approach (in the project development time scale) – and in that way to can make the project completion to be earlier than before when you use the traditional flow.
Q11: Is it possible to integrate external SystemC pre-compiled IPs and simulate it with Questa/Visualizer?
Yes, it is possible. Of course, if you have the IP sources it can be compiled as part of Questa design. If it is available as pre-compiled shared library or archive, then it can be done but you need to make sure that it is compiled using gcc version which is compatible with the versions supported by Questa and also that it is compatible to the SystemC version supported by Questa (in 2024.x versions of Questa it is 2.3.4). And for using external SystemC IP models you’ll need to have the interface of the external IP (usually it is a header file) that will be used for its integration and instantiation in the design.
Q12: Is it possible to create shared libraries as the output or result of sccom command?
Yes, you can create intermediate share libraries for your SystemC design compilation but then you’ll need to link it (using “sccom -link …” command) for one systemc.so file which will be used for the simulation.