Aprisa Die Shrinkage in Aprisa

2024-07-13T18:21:46.000-0400
Aprisa

Summary

This Support Kit introduces methodology to reduce the area of the chip by improving overall utilization of chip at floorplan stage. Die shrinkage via floorplan minimization is a process used in semiconductor design to make the chip smaller by carefully organizing its components without compromising its performance or functionality. This process starts of reduction in size of chip area starts with the first physical implementation stage, floorplan, by rearranging the functional blocks—such as memory cells, input/output (I/O) circuits, and logic gates—inside the chip's physical boundaries. However, the area of a chip refers to the physical space it occupies on the silicon die. Smaller chips allow for higher packing densities, leading to cost savings and increased functionality. This is why minimizing chip area is one of the crucial PPA metrics to consider.


Details

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In this Support Kit, the goal is to reduce the area of the chip by improving the utilization ratio of the chip using 3 different methods using both the command line and GUI.

1.   By Ratio

2.   By Size

3.   By Co-ordinates

 

Estimated time to complete the Support Kit: 30 to 45 minutes.

Version Information:
AP 22.R1 and above.

Note:
 Ensure that the downloaded test case is saved to a proper working directory and that you provide the full path when loading the project after invoking AP.

 

 

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KB Article ID# KB000133521_EN_US

Contents

SummaryDetails

Associated Components

Aprisa P&R Ap SW