Tessent How to prevent the tool from automatically loading the ICL files of a design?

Tessent Shell Flow



Tessent automatically loads the ICL files of modules If the RTL of these modules in the design is read and compiled.

In order to prevent this, you can use the following command:

set_design_source -format icl -search_design_load_path off

This command prevents the tool from adding the ICL files when reading the RTL files as by default the tool reads the ICL files in the directories when Verilog/ VHDL modules are loaded.

KB Article ID# KB000132001_EN_US



Associated Components

Tessent Shell Environment