Aprisa Identifying cells having highest delay in a timing path.

Debugging timing:

• The most important step while debugging timing is to look at the timing report and identify the cells having highest delays.
• Cells with highest delay will lead to setup violation, making it difficult to close the timing.
• If the cells with highest delays are identified and replaced with cells with lowest delays the timing can be closed.

At which stage the timing issues need to be handled?

After PLACE/CTS/CTS_OPT/ROUTE stages we check and try to fix timing.

Steps to be followed:

• The script provided here helps to print all the cells along with the path group to which it belongs, whose delay value is greater than the specified threshold.
• In this manner, we can identify those combinational set of cells which were resulting in higher delays and replace them with other cells of same footprint.
• Using the below attached script, we can also get the target pins, which are nothing but the pins of the cells whose delay is greater than the specified threshold. These target pins can be given as a switch in place_opt command. Placer will try to optimize these cells and improve the timing further.

Example Usage:

% source printing_cell_dly_greater_than_threshold.tcl

The output here contains the pin name, cell name, cell delay, corresponding lib cell and the path group to which it belongs.

Output:

Explanation:

The above script tries to compare the delay of each cell with the delay specified by the user and prints the output, if the delay is greater than the specified threshold. In addition to the cell delay, the pin name, lib cell name are also printed using the other properties of the cell. As a part of next step, user can use the collection of these pins and provide it in the place_opt command to enhance timing.