Calibre Calibre 3DSTACK: Bringing a 3rd Dimension to IC Verification

Summary

The Calibre 3DSTACK tool extends Calibre die-level signoff verification to complete signoff verification of a wide range of 2.5D and 3D stacked die designs. Designers can run signoff DRC and LVS checking of complete multi-die systems at any process node using existing tool flows and data formats. In this Calibre webinar, you can gain valuable insights into how to use 3DSTACK for your full-stack verification when working with advanced packaging and multi-die package manufacturability.

Details

Q&A  
 
Note: 
1. Thank you all for the questions during the webinar! Below is the transcript of the questions and answers.
2. If more support is needed for any of the issues you are facing, please open a support case at  https://support.sw.siemens.com/en-US/support-case/open

Q) What licenses does the user need to run Calibre 3DSTACK? 
A) One of the advantages of using 3Dstack is the absence of additional licenses. Having Calibre DRC/DRCH, LVS/LVSH & calibredrv licenses are enough to run Calibre 3DSTACK. 
 
Q) During the webinar you mentioned that die and interposer layouts are in GDS and OASIS format. What other formats are also the Calibre 3DSTACK supported? 
A) Calibre 3DStack is supported with GDS and Oasis formats, as well as LEF and DEF formats. There is also a utility that can convert ODB++ to GDS or OASIS for 3dstack usage. Please find the ODB++ to GDS converter utility link below: 
Calibre 3DSTACK User's Manual (siemens.com) 
 
Q) How does the interposer ensure the connection between dies, what is inside the interposer? 
A) In 3D IC technology, an interposer is a passive component that typically contains through-silicon vias (TSVs), which vertically connect different layers. The interposer itself may also include additional passive components like capacitors and resistors. Its primary function is to provide a platform for connecting and stacking multiple dies or integrated circuit layers. 
 
Q) Why should die be placed on an interposer face down? 
A) It is known that the dies must be connected to the outside world by the highest metal layer. The dies should be placed face down so that the last metal layer can connect through the interposer. 
 
Q) Besides the mentioned SPICE and VERILOG formats, what other source netlist formats are supported by the Calibre 3DTACK? 
A) Besides the SPICE and Verilog formats, source netlists are also supported in MGC and CSV formats. Different utilities can convert CSV-formatted spreadsheets and AIF into SPICE or GDS and OASIS for use in Calibre 3DSTACK.
 
Q) What are the key differences between 2.5 and 3D IC? 
A) 2.5D IC: Involves stacking multiple dies or chips on a common silicon interposer 
3D IC: Involves stacking multiple dies directly on top of each other, creating a true three-dimensional structure. 

Q)  Does the 3d stack rule file come from the foundry, like other verification tools? 
A)  Foundries typically provide designers with rule files that contain information about the allowed dimensions, clearances, tolerances, and other specifications for the 3D stacking process. However, the designers can also make appropriate changes in the rule file depending on the design and challenges that they are facing. 

Q) During the demo I noticed that the run on the design took several minutes but the layout was not big. I’m wondering how long it will take to run a full chip and if would it be possible to run it with the distributed run. 
A) The run time mainly depends on how many errors/violations are in the design. Also, the complexity of the design is a crucial factor in its velocity. And YES, Calibre 3dstack also supports distributed processing. 
 
Q) Is the run also supported via the GUI mode? 
A) As with the other verification tools 3DSTACK also is supported to run through Calibre Interactive GUI. 

Q) Is it possible to use black box statements for some of the IPs in the design similar to the LVS? 
A) Yes, we can use black box statements like LVS. We can use the black box mode to check connectivity from die to die, without considering anything inside the box. Black box mode in 3dstack depends on the information defined in the rule deck and netlist, if the internal connectivity of the dies is not defined, and not defined in the netlist, black box mode will be used. 

Q) What will happen if we run a 3d stack with incorrect DRC or LVS? 
A) In 3DSTACK for the DRC and LVS checks, we are using the die’s external layers. So even if some violations inside the die can be detected with LVS/DRC checks if we are using the external layers for 3D IC verification it is possible to get clear results after the run. In case the internal connectivity of the dies is considered (white box mode), the dies must be LVS clean. 

Q) Can we do stack die verification (without an interposer)? 
A) 3DSTACK has an option for a stand-alone check, which can be used for a separate die. You can do verification between two dies without involving an interposer, and you can create a check for each pair of dies.  

Q) Where is the documentation for 3DSTACK? 
A) The documentation for Calibre 3DSTACK you can find in the Support Center, also you can use the following link which will redirect you to the manual:  
Calibre 3DSTACK User's Manual (siemens.com) 

Q) What is the maximum number of layers in today's chips? 
A) Each foundry has its own set of stacks defined by both technology and its customers’ requirements. Routing metals can reach up to 20 layers including the stack’s front end’s routing layers (local interconnects) in addition to the vias connecting between them.  
However, the exact number of layers can vary based on the specific technology node, manufacturing process, and the type of chip (e.g., logic, memory). 
 
Q) Is it possible to use a Calibre 3DSTACK with 3rd party tools? 
A) Currently, the 3DSTACK is not supported for using 3rd party tools. However, the generated results can be used for running mPower and XSi flow.  

Q) What is the minimum Calibre version for running Calibre 3DSTACK? 
A) The minimum version for Calibre 3DSTACK is 2015.3. As we are continuously improving the tool, we always recommend using the latest version for your verification. 
 
Q) The introduction mentioned creating PEX files for the 3D stack. I did not see that covered. 
A) We can specify the export_layout command to generate an annotated GDS and extraction data for a specified portion of the assembly. More info about the generated results and the arguments can be found in the following link: 
https://docs.sw.siemens.com/en-US/doc/852852053/202303075.calbr_3dstack_user/idfe3ea413-465b-45fd-8918-3cb616f852c2?audience=external 

Q) Does 3DSTACK do the interposer routing for multi dies? 
A) 3DSTACK does not do any routing itself, this is done by the designer or P&R tools. 3DSTACK is only used for the verification analysis. 
So, designers can use 3DSTACK during this routing to validate the connections, but it does not generate any routing by itself. 

Q) How to use the 3d stack for one die having the shrink and another not having the shrink? 
A) In 3DSTACK, you have the option to assign a shrink factor to each die separately, or to the stack as a whole. For instance, if you are working with two dies, and one requires shrink while the other does not, you can specify the shrink factor for only the die that needs it. This factor will then be applied exclusively to that die during placement. 
-mag factor (in the stack definition), Optional argument, and value set that specifies a magnification factor by which to expand or shrink the placement. Coordinate data in the object is multiplied by the specified factor. 
 
Q) if your die/interposer designs are not clean, what happens? It might be necessary to do early DRC/LVS when these designs are not clean, so what do you do?  
A) YES, it is required to do the DRC/LVS analysis for each die separately, because if there are any DRC/LVS violations, they will not be detected in the 3DSTACK stage. Thus, you need to have a clean die with no DRC/LVS violations for each individual die. 
 
Q) Can you show a sample of the checks you run? Is it automatically generated or manually coded through the fab?
A) The rules used for the demo are not generated automatically but manually coded. 
XSi can help to automatically generate the 3dstack+ rule deck. 
 
Q) How does this tool ensure multiple dies are placed properly? Is it through bump alignment check or any other technique introduced? 
A) To ensure that the dies are placed properly you can do the bump alignment check. Some of the users prefer doing alignments of the boundaries of each type and this is the way the tool ensures that multiple dies are placed properly. 
 
Q) Is 3D LVS the only flow? Or do we also have 3D DRC checks as well? 
A) As was shown during the webinar 3DSTACK supports both LVS and DRC checks. During the webinar, the results were generated for the 3D DRC flow. 
 
Q) In 3D IC LVS flow - Why transistors, and active devices are NOT allowed to define them inside the source netlist? Can you please explain this point further?  
A) The only thing that should be taken care of in 3D IC LVS flow is the external pins of the dies. As when you are reaching the 3DSTACK stage we suppose that you already have complete clean DRC and LVS checks for each separate die. That is the reason why we only need their external pins. 
 
Q) Is the interposer a TSV? 
A) The interposer typically includes Through-Silicon Vias (TSVs) as a key component.  
In addition to Through-Silicon Vias (TSVs), interposers in 3D IC technology typically contain several other elements such as wiring and metal layers, dielectric layers, bump or microbump connectors, passive components (resistors, capacitors, and inductors). 

Q) Are TSVs connected to micro bumps? 
A) Yes, Through-Silicon Vias (TSVs) are often connected to micro bumps. 
 
Q) Are only flip chip designs allowed to stack or are wire bond designs also allowed to stack? 
A) While flip chip designs are more commonly associated with 3D IC stacking due to their inherent advantages in terms of interconnection density, thermal performance, and signal integrity, it is possible to stack wire bond designs as well. 
 
Q) What is a good example of a 3D IC in the market? 
A) Intel's Foveros technology is an example of a 3D IC in the market. Intel has applied Foveros in products such as the Lakefield processors, including the Intel Core i3, i5, and i7 processors. 

Q) How does calibre drv differentiate c4 bumps and micro bumps? 
A) Differentiation between C4 bumps and micro bumps would typically be based on specific design rules or properties defined in the rule deck used for the verification process. These rules may include parameters such as size, pitch, spacing, and layer information. 

Q) Let's say we have 2 dies with nothing inside both dies but it has an interface layer. As long as we define the interface nets of both the die. Can we use 3D LVS flow in this case? 
A) In most cases, we will deal with what you have described: dies that have only their external layers defined. Even if these dies are not empty inside, we will ignore everything within them unless there is a specified connection to the external layers. 
So, 3Dstack will check the text labels on the interacting layer and ensure that they are the same, and if the source netlist exists, physical connectivity will also be compared to the source netlist 

Q) Is it possible to do a Top-down approach 2.5D or 3D approach? 
A) Yes, it is possible to use a top-down approach for both 2.5D and 3D integrated circuit designs. In fact, the top-down approach is commonly employed in these scenarios. During the LVS and DRC in 2.5D and 3D IC designs, the focus is primarily on the external connections and interfaces of the separate dies. The internal connections within individual dies are typically not the focus unless they have specific interactions with the external layers. 

Q) How do you handle high heat generation/dissipation in 3Ds? 
A) Packaging plays a crucial role in thermal management for integrated circuits, including 3D ICs. Proper packaging solutions can significantly contribute to heat dissipation, reliability, and overall thermal performance. The 3DSTACK tool is not designed for handling or checking heat generation/dissipation in 3D ICs.   
Sahara (thermal analysis tool) can be used for this purpose. 

Q) Please provide a test case to try the 3DIC applications in Calibre. 
A) We will work on preparing a full downloadable demo in a support kit. It will be posted under this link: 
https://support.sw.siemens.com/en-US/knowledge-base/MG620170
Once it is ready, we will follow up with you. 
Also, you can use the following link to access the virtual lab that allows you to work with 3DSTACK flow. 
https://trials.sw.siemens.com/high-density-advanced-packaging-trials/ 

Q) Can you please show the content of the 3D rule file?  
A) We will follow with a completed demo in a support kit which will contain all the necessary files required. 

Q) Do you have an example test case that we can use to try and run the tool?  Something that demonstrates what should go in the rule file? 
A) We will follow up with a completed demo in a support kit. 

Q) Can you do a webinar on xSI also? Sorry for the repeat question but my webinar reset again, and all my questions and answers got deleted. 
A) We have a virtual lab that prospective e-customers can access to work through the XSI - 3DSTACK flow.  It runs complete design from setup to verification, debug, and ultimately a clean run. On the trials page, there is another virtual lab that is focused on XSI. 
Please find the link below: 
https://trials.sw.siemens.com/high-density-advanced-packaging-trials/ 
 Also, please find the link to the KBA for XSi flow below: 
https://support.sw.siemens.com/en-US/product/852852053/knowledge-base/MG611344 
 
Q) Can you do an xSi presentation also? 
A) We have a virtual lab that prospective e-customers can access to work through the XSI - 3DSTACK flow.  It runs complete design from setup to verification, debug, and ultimately a clean run. On the trials page, there is another virtual lab that is focused on XSI. 
 Please find the link below: 
https://trials.sw.siemens.com/high-density-advanced-packaging-trials/ 
 Also, please find the link to the KBA for XSi flow below: 
https://support.sw.siemens.com/en-US/product/852852053/knowledge-base/MG611344 
 
Q) Please send us a notice when the demo file becomes available to download.  
A) Will follow up once it is ready, Stay Tuned. 

Q) Please do some webinars on the PEX topic... 
A) We have started the PEX series, this is the link to our first PEX webinar: 
https://support.sw.siemens.com/en-US/product/852852053/knowledge-base/KB000122828_EN_US  
 and more to come. 

Q) A webinar is required for PEX using Calibre 
A) We have started the PEX series, this is the link to our first PEX webinar https://support.sw.siemens.com/en-US/product/852852053/knowledge-base/KB000122828_EN_US  
  
Q) Regarding the creation of the top virtual netlist, if I don't have the package layout, should I       exclude the package pins in the source netlist? 
A) You don't need to have the package layout beforehand; it will be the output of the 3DSTACK run. Once you describe the dies and packages, the final package will be assembled according to your instructions in the rule file. Therefore, in your top netlist, you should only specify the dies and connections between them. 
 
Q) We heard that 3DBlox2.1 would be released. What is the difference between 3DBlox and 3DBlox2.1? we learned that TSMC would be releasing the SPEC by the end of December 2023.  calibre tool supports that spec or any tool enhancements going on to support that? 
A) We are unable to disclose that information until it becomes publicly available.