Q: When simulating via structures for high-speed SerDes, how much area should we include in the simulation beyond the vias? Is symmetry important? Are round vs square areas preferred? video time-point 17:15
A: The 3D area needs to include the return path (vias) and the fields around the signals being modeled. Also, ensure that the boundary allows for TEM waves where it intersects the signal traces.
Q: Please introduce some advantages compared with other tools. video time-point 20:40
A: Integration in the analysis flow and a uniform GUI are major advantages for HLAS.
Q: How to estimate time and resources needed for solving? Currently, HLAS only has a progress bar which is not linear. video time-point 22:20
A: it is impossible to correctly estimate the simulation time of a solution. You can observe the time to simulate the first few frequencies and extrapolate the time from that time.
Q: Is it possible to simulate a DDR memory interface together with return current and PDN? Can we assign IBIS models? What issues can be found during this type of analysis in comparison with conventional SI and Timing analysis done in standard HyperLynx? video time-point 25:00
A: Use HLAS behind BoardSim to create the PDN + signal model. Then run the power-aware simulation in the DDRx Batch Wizard.
Q: I have a design with 48 Layers. When using the 3D Area wizard it takes all the layers by default, but my via span is only on the few top layers. Is there a way to tell the wizard to ignore those not-used layers? video time-point 27:10
A: You can edit the parameters of the 3D area to omit the layers that are not relevant to the model.
Q: How can we simulate a DDR4 DRAM or SERDES current return path including correct IBIS models in the Advanced Solvers? We would then like to visualize the current density in 3D graphs to pinpoint the problem areas if possible. video time-point 28:05
A: See the Support Kit in the Support Center article
MG621713. The visualization of current density is done manually with the HLAS GUI.
A: This solution is possible in some cases in HLAS. It would most likely be very computationally intense.
Q: Does HLAS implement Adaptive Meshing to ensure a sufficient level of accuracy of the S matrix it generates? video time-point 32:40
A: HLAS does not need adaptive meshing because it is optimized for PCB or package (planar) layout geometries. The correct mesh for these geometries can be determined before starting the solver.
Q: What is the difference between Full-Wave solver and Full-Wave Solver HPC? video time-point 35:00
A: HPC can use multiple threads and cores in your computer. This feature uses multiple licenses.
Q: Is it possible to extract an S-parameter block for a given power domain from the layout with all power net ports shorted and all ground nets shorted and just output a 1-port S-parameter block to simulate in an external tool? video time-point 35:45
A: This is precisely what Lumped Decoupling Analysis creates. If you need more flexibility, you can do the same configuration in the Hybrid solver.
Q: How do I get through sign-off and compliance on a high-speed ser-des diff pair on a crowded board without running full wave on the entire design? video time-point 37:25
A: We recommend using 3D areas in BoardSim to solve the appropriate areas in 3D and then run Compliance Wizard or IBIS-AMI simulations on the channels.
Q: From an IC packaging standpoint, what are the minimum geometries that can be analyzed using the HyperLynx Advanced Solvers? Are 0.5um width/clearance technologies doable? video time-point 39:25
A: There is no practical limit on the minimum resolution of the 3D model. The complexity of the geometry is a greater factor in creating more mesh elements.
Q: Please provide me a step-by-step procedure for the application of Advanced Solver with 3D EM Analyzer for a differential pair of lines (e.g. Video signal differential GMSL_link_SIOA_N & P), as well as single-ended line GMSL_Link_CAMx.etc. as a white paper, PPT, PDF, etc. video time-point 41:10
Q: Q1: 3D solving in a stack-up with several dielectrics stacked on top of each other massively increases computation time. Maybe not surprising?
Q2: Using the automatic area creation feature does a good job of finding transitions but creates complicated areas. Does this affect computation times compared to manually drawing a simple rectangle? video time-point 41:35
A: 1: The mesher uses the boundary element method, so defining another boundary between dielectric layers increases the boundary mesh elements.
2: A smaller area generally has fewer mesh elements and thus will run the solution faster.
Q: How to model the interconnects on a PCB and evaluate the frequency and time-domain measurements?
A: The easiest method to use the Advanced Solvers for full net modeling is to use the 3D Areas feature in BoardSim. This creates full 3D EM models of the areas that really need to have advanced models. A second option is to import the full layout into Hybrid solver, extract the S parameters of the net or nets of interest, and connect the resulting Touchstone file as desired in LineSim for the circuit simulation.
Q: 1) Regarding the electromagnetic interaction between the PCB and package, is it possible to simulate them separately and subsequently connect the S parameters of the PCB and the S parameters of the package? Or is the interaction between the two lost and so is it better to perform an electromagnetic simulation considering both PCB and package at the same time?
2) If we have a system in which the current has a different return path depending on the phase it is in, and we want to perform a co-simulation with the extracted S parameters and the rest of the electrical circuit, is it necessary to run two different electromagnetic simulations specifying a different return path and use one extraction rather than another depending on the case in which we are?
A: 1: It is feasible to generate S parameters of separate designs and then connect them in a circuit simulation. Be careful to place the ports as much as possible where the field propagation is TEM. As expected, this method cannot account for field coupling that might actually happen between the 2 designs.
2: The return path can be correctly modeled and simulated by placing a port on each phase of the multi-phase VRM.
Q: 1) Does HyperLynx Fast3D provide capabilities for detailed modeling of individual components to calculate parameters such as mutual inductance?
2) How does HyperLynx ensure accurate modeling and extraction of parasitics?
3) Could you share specific instances or use cases demonstrating the practical applications of the HyperLynx Advanced Solvers?
A: 1) Advanced Solvers models the geometry in the 3D model, so if you enter the geometry of components into the 3D model, they will be included in the results. 2) The accuracy of the Advanced Solvers is constantly being evaluated and improved. The user still needs to have an idea of what to expect in order to determine if the results are acceptable. 3) The practical applications of the Advanced Solvers are pretty much any modeling of PCB or planar IC package layouts.
Q: If you are doing a PCIe 3.0 simulation in a routed board, how should I do the extraction and run the simulation to ensure the traces meet the PCIe 3.0 requirements?
A: The most efficient method for this scenario is to generate 3D areas on the nets to simulate, solve the 3D areas with the FullWave solver, and then run the Compliance Wizard, or IBIS-AMI Simulation if you have the models.
Q: Which tool to use to do an S-parameter extraction for SERDES simulation?
A: FullWave and Hybrid solvers produce S parameters. The most effective method for this situation is to solve the 3D areas on the SerDes channels and then simulate them with IBIS-AMI models.
Q: Is there an easy way in the Advanced Solvers to modify diff pairs and see the changes in simulation results? For example, fixing the length matching jogs that go around ground vias asymmetrically.
A: It is possible to edit the geometry in the Advanced Solvers, but it is not very efficient. For a small change like this, it might be reasonable. A better method is to create a sweep of the geometry using 3D Xplorer.
Q: We have a cluster that is NOT one of the "supported" clusters that HLAS supports. I wanted to add HLAS integration to our cluster, and it seemed to be impossible. I also wanted to add integration within the seamless BoardStation blind EM simulation capability. There just does not seem to be configurability within these tools robust enough to do custom integrations.
A: This issue is outside the realm of this webinar. Please continue to work with your local field AE and customer support to pursue a solution in job distribution.
Q: I accept that the "time to solution" is not reasonably possible to be provided. I need a scripted way to estimate the memory when creating a remote cluster simulation, so the memory requests are determined automatically. That can be used to resubmit the job that has the required amount of memory. Removes manual estimate processes. Automation within HLAS and/or BoardSim to do this to export the needs would help.
A: We agree that this would be useful. Stay tuned for developments around job distribution.