HyperLynx DDR5 Clock De-Skew

HyperLynx Marketing SI/PI


HyperLynx VX.2.14.1 and later support DDR5 Clock De-Skew -What is DDR5 Clock De-skew? DDR5 DRAMs have a DQS Clock Tree delay- this is different than DDR4, and it must be taken into consideration when building the equalized eye diagram for the receiver on write cycles. The memory controller has equalization that causes delay, so clock de-skew is needed for read cycles. -What kind of IBIS-AMI buffer models do I need to simulate Clock De-Skew in my DDR5 batch simulations? -How do I enable Clock De-Skew in my DDR5 batch simulations? -What files are created when Clock De-Skew simulations run?


What: Clock (DQS) De-Skewing centers the DQ eye for DDR5.
In the DDR5 hardware, the Memory Controller sweeps delays and Vref at power up to find the right amount of delay to add to the DQ signals for the eye to be centered in the mask. The DQS signal is delay matched to the clock, therefore the DQ signal must be delayed to center the DQ eye. This balances setup and hold. For write cycles, the memory controller adds delay at the transmit side. For read cycles, the memory controller adds delay at the receiver side.
Whereas with DDR4 a perfectly delay matched DQS and DQ (memory controller die to DRAM pin) would not need much if any de-skew. In contrast, DDR5 has both extra delays from the equalization and also a DQS clock tree delay not seen in DDR4. To reduce power consumption, DDR5 has a built-in DQS clock delay. This delay is due to buffering for fan out of eight DQ latches, and it is described in the DDR5 JEDEC specification as tRX_DQS2DQ. Because of the delay, the transmitter must compensate and launch the DQS early compared to the DQ. The DQs must be de-skewed from the DQS signal.
 Unlike DDR4, DDR5 has equalization (Decision Feedback Equalization) for the DQ signals in order to run at higher speed grade. To model this equalization in a simulation  IBIS-AMI models are needed.
Since the DQ signal is clocked by the DQS, the simulation needs to allow the DQ signal to use the DQS signal as a forwarded clock. The version 7.1 IBIS specification includes the new IBIS-AMI reserved parameter  named Rx_Use_Clock_Input for receiver IBIS-AMI models for DQ signals. If the parameter value is “Wave”, HyperLynx will use the clock_times values (for the DQS strobe crossings)  from the DQS Rx AMI_GetWave call as the clock_times values in the call to the DQ Rx AMI_GetWave. This incorporates the delays into the simulation.

How to Use the Clock De-Skewing feature in the VX.2.14.1 and later DDRx Wizard:

  • Assign IBIS-AMI receiver models with reserved parameter  Rx_Use_Clock_Input that allows  “Times” or “Wave” value setting
  • DDRx batch simulation
  • DDR5 setting
  • Time-Domain IBIS-AMI flow setting
  • The receiver IBIS-AMI model reserved parameter setting is “Times” or “Wave”
  • In the Leveling and Calibration page, select “Automatically run simulation 2 times” option
  • The memory controller De-Skew granularity is set by the “samples per bit” setting on the Simulation Options page (default = 32).

How to check that the DDR5 batch simulation included Clock (DQS) De-Skewing:
When the batch is complete, go to the report folder for the batch run.


KB Article ID# KB000128455_EN_US



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