Xpedition Enterprise Using IBIS Models for Functional Analysis in Xpedition® AMS

Abstract

IBIS (Input/Output Buffer Information Specification) is a method of modeling circuits for functional or signal integrity analysis. SPICE models contain transistor-level information, whereas IBIS models are behavioral models consisting of tables that specify current/voltage (I/V), voltage/time (V/T), and parasitic behavior at each pin. IBIS models are generally less accurate than SPICE models but are usually faster and allow vendors to avoid divulging proprietary information about designs.

In Xpedition^® AMS, IBIS models can be mapped to symbols so that simulations can account for real-world and parasitic effects. These simulations can be used to verify that the functional behavior of the circuit is acceptable when these effects are introduced.

At the end of this Support Kit, you will be able to assign IBIS models to components in the schematic and simulate them using Xpedition^® AMS to verify functional behavior.

Estimated Time to Complete: 30-45 minutes

Version Information: Xpedition AMS VX.2.13

Directions

1. To access the test case, navigate to
   <Xpedition AMS install path>\SDD_HOME\sim\systemvision\tutor
   and copy the folder IBIS_Tutorial to a convenient location on your disk drive.
2. Launch the Xpedition AMS application from the Start menu. In Xpedition AMS, select File > Open > Project and navigate to the copied IBIS_Tutorial folder from the previous step. Open the file named IBIS_tutorial.prj.
3. This will open a schematic of a four-bit counter, as shown in the figure below:
   

4. To begin, simulate the circuit without parasitics for 325 ns to observe the ideal desired behavior. Select Simulation > Simulate and fill out the Simulation Control dialog as follows:
   
   Click OK to run the simulation.
5. The Waveform Analyzer will appear with the simulation results. From the Waveform List, open and observe the signals named q0, q1, q2, q3, and clk. These signals represent the four bits of the counter and the clock signal:
   

Part 2: Map IBIS Models to Individual Components

6. We will now map IBIS models to the two AND gates individually. Right click on the symbol named AND1 and select Edit Model Properties. This will open the Model Properties dialog.
7. In the Model Properties dialog, keep the Simulation Model Type set to ‘VHDL’ and click the IBIS Model button. In the IBIS Library box, click the ‘…’ button and navigate into the folder named IBIS_models in the IBIS_tutorial folder. Select the IBIS model named SN74LS08_and.ibs and click Open.
8. The IBIS Model dialog appears. To map a Symbol Pin to an IBIS Device Pin, click on an entry in the Pin column and select the desired pin number from the drop-down menu. Map the pins as shown below:

           

9. Click OK to finish mapping this component.
10. Repeat steps 6-9 for the symbol named AND2.

Part 3: Map IBIS Models to Components using the Setup Schematic Simulation Data Wizard

11. We will now map IBIS models to all JK flip-flop symbols at the same time using the Setup Schematic Simulation Data wizard. Firstly, make sure that no symbols are currently selected. Then select Simulation > Simulation Data > Set Up Schematic to open the Setup Schematic Simulation Data on Active Sheet wizard.
12. Check the box next to Digital:JKFF and click Assign/Edit Models.
13. In the Model and Symbol Wizard, under the Select Source tab, Select VHDL-AMS as the model type and check the Add IBIS Model… box, as shown below.
    
14. Click Next to proceed to the Select/Create Model tab and do not make any changes. Click Next to proceed to the Map Symbol Pins to Model Ports tab and ensure that the Model Port Names are mapped to the Symbol Pin Names as shown below.
    
15. Click Next to proceed to the Set/Map Parameters tab and do not make any changes.
16. Click Next to proceed to the IBIS Model tab. In the IBIS Library box, click the ‘…’ button and navigate into the folder named IBIS_models in the IBIS_tutorial folder. Select the IBIS model named 74LCX112MTC_JKFF.ibs and click Open. Select LCX112 in the IBIS Device box.
17. The Model and Symbol Wizard appears. Assign the Symbol Pins to the IBIS Device Pins as shown below.
    
    Click Finish in the Model and Symbol wizard. Click Finish in the Setup Schematic Simulation Data wizard to map the IBIS Model to all instances of the JK flip-flop symbol in the schematic.

Part 3: Simulate the Circuit with Mapped IBIS Models

18. Select Simulation > Netlist > Netlist Settings. Select Complete Design under Scope and check the Include IBIS box. In the IBIS Modeling field, we can select which corner the model operates in: Slow-Weak, Typical, or Fast-Strong. We will select Typical for this demonstration.
19. Run the simulation by selecting Simulation > Simulate and keep the same parameters as the simulation from Part 1. Click OK in the Simulation Control dialog to run the simulation.
20. The Waveform Analyzer appears. From the Waveform List, open and observe the signals named q0_d_control, q1_d_control, q2_d_control, q3_d_control, and clk.
    
    Note that q2_d_control is now delayed by two clock cycles. In addition, q3_d_control falls below the voltage threshold for a ‘1’ bit, so it is in the ‘X’ state instead of HIGH. The functional behavior of the circuit is no longer acceptable due to the parasitic effects introduced by the IBIS models.