The VX.2.14 release includes:
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Significant improvements for DDR5 interface design & verification
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New protocol & simulation support for standards-based serial link design & verification
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Improved integration with Xpedition Engineering Data Management, or EDM.
HyperLynx DRC - Rules-based Design Verification
HyperLynx DRC includes a new via length rule that checks the combined length of vias in a net and improvements to multi-layer creepage rules and acute angle rules.
A new area crop capability speeds checking of complex boards by allowing users to identify a portion of the board to be checked, then creating a new, smaller board to run the selected rules against.
HyperLynx SI/PI - Signal and Power Integrity
DDR5 interface design and verification
HyperLynx SI now provides system-level simulation for DDR5 registered DIMMs. The DDR wizard has been extended to include support for Registered Clock Devices, or RCDs, present on RDIMMs.
HTML reporting has been improved to include a summary page and consolidate information that previously spanned several tabs.
Serial Link interface design and verification
HyperLynx SI also includes SerDes Compliance support for 9 additional protocols. New ladder filter package models and raised cosine filter support lets HyperLynx verify serial channels based on the latest standards.
The IBIS-AMI simulation wizard has been enhanced to improve specification and management of jitter parameters, ensuring integrity of jitter data provided by the AMI silicon vendor.
Engineering Data Management (EDM)
Improved integration with Engineering Data Management, or EDM, in HyperLynx VX.2.14 lets you selectively check data into the EDM vault, allowing you to save only the data you really want to retain as part of the project record.
With new features and enhancements across the VX.2.14 release, HyperLynx helps you create, optimize and verify your designs quicker than ever before.
Watch a series of short videos describing all these HyperLynx VX.2.14 featuresQ&AQ: How do I find the workshops?
A: In SupportCenter, Set your product to Hyperlynx then find the Getting Started tab. In Geting Started there is a tile for "Workshops for Analyzing High Speed PCB Designs. Here is the link: https://support.sw.siemens.com/knowledge-base/MG608240
Q: I noticed in the slides that the eye mask for DQ and Control signals was different. Is that right?
A: Yes, for DDR5 the DQ eye is diamond shaped and the command eye mask is rectangular.
Q: I have a Xilinx Versal model with S-Parameter package and another S-Parameter file. Can I use this in the AMI batch wizard?
A: Yes, the is a knowledgebase article that tells how to convert it to IBIS 7.0 format. The link to the article: https://support.sw.siemens.com/knowledge-base/MG612211
Q: For SerDes Compliance, when you say "Protocols and Variants", what are "Variants"?
A: "Variants" are different flavors of a given protocol - for example, some PCIe protocols have add-in card only, system card only and end-to-end variants, and some Ethernet protocols have different variants depending on where you are probing the signal.
Q: If you do channel simulation you have all this wonderful protocols as example. Do you have also for DDR example Modules or slots
A: There is a Support Kit for DDR: https://support.sw.siemens.com/knowledge-base/MG618350 and a Workshop for DDR on the Workshop page: https://support.sw.siemens.com/knowledge-base/MG608240
Q: Why is UFS (UNIVERSAL FLASH STORAGE) protocol not supported in the protocol list?
A: This has not been requested by enough users, and has been lower priority than other protocols. This request has been submitted to the Ideas site (and our product technical marketing team): https://community.sw.siemens.com/s/idea/0874O000000HD8dQAG/detail Please vote for this Idea.
Q: New crop feature in HyperLynx DRC can be automated?
A: Yes: Document.SaveAreaCrop(<fileName>, <boundary geometry>)
The Geometry should be defined by user. Please note that the project and constraints will be saved along with the layout file.
Q: Do we plan to have smith charts in any of the future releases? I find it as a very useful result based on my experience with other EDA tools
A: This has not been requested by users, and it has been submitted to the Ideas site: https://community.sw.siemens.com/s/idea/0874O000000bsKXQAY/detail Please vote for this Idea.
Q: Can we create our own SerDes Standards based on vendors models? AMD INTEL etc.
A: It is possible but requires work understanding the protocol specification details as well as how to create the SerDes wizard .cnfg file. We have documentation on this and it is an advanced topic.
Q: Can I run Hyperlynx 2..14 with Expedition VX2.13
A: Yes- the two are compatible standalone. To run XAC (Xpedition Analysis Control) you need to have both tools the same version.