When including SPICE models in your project for simulation in Xpedition AMS, there are several important considerations to keep in mind.
When including SPICE models in your project for simulation in Xpedition AMS, there are several important considerations to keep in mind:
You can simulate a design using SPICE models only, VHDL-AMS models only, or a combination of both.
Xpedition AMS allows you to choose between VHDL-on-top or SPICE-on-top netlisting modes. The default mode is SPICE-on-top, which generates a SPICE netlist for simulations.
In the SPICE netlist, Xpedition AMS adds a prefix to the reference designator for each instance of a VHDL-AMS model. It uses the letter "Y" for VHDL-AMS models and the letter "X" for hierarchical schematics.
Here's an example of a SPICE-on-top netlist generated for the "ex_rlc" testbench, which uses four VHDL-AMS models: resistor, capacitor, r, v_pulse. Note the prefix designation for each reference designator:
YR1 RESISTOR(IDEAL) GENERIC: RES="3.0" PORT: VINPUT VMID
YL1 INDUCTOR(IDEAL) GENERIC: IND="1.0E-3" PORT: VMID VLOAD
YC1 CAPACITOR(IDEAL) GENERIC: CAP="10.0E-6" PORT: VLOAD 0
YV_PULSE1 V_PULSE(IDEAL) GENERIC: AC_MAG="1.0" DELAY="1MS" PERIOD="100MS" PULSE="5.0" TI2P="10US" TP2I="10US" WIDTH="10MS" PORT: VINPUT 0
For performing multi-run analyses such as parameter sweeps, DC sweeps, or Monte Carlo simulations, the netlist of the testbench must be in SPICE format (SPICE-on-top).
Xpedition AMS includes a Spice Syntax Checker that is enabled by default. It checks and attempts to correct syntax issues in Spice models when they are first used in a project.
You can toggle the "Check syntax" feature and manage notifications from the Spice syntax checker in the Simulation > Settings > General > AMS tab.
You can change the netlisting mode by selecting the Simulation > Settings > Testbench menu item and modifying the toplevel file type. Further information is available in the "Testbench Options" documentation.
Xpedition AMS provides several symbol libraries containing primitive SPICE models for your convenience.
Contains components like resistors (R), inductors (L), capacitors (C), and voltage sources (V_SIN). Double-clicking on these components allows you to specify model parameters.
Contains symbols that are automatically parameterized when associated with specific models. You can select the desired model from the Navigator pane and drag it onto the schematic canvas.
Contains opamp and comparator components. These components are automatically parameterized when a specific model is specified. You can choose the desired comparator model from the dropdown menu in the symbol properties or directly drag the model onto the schematic canvas.
Avoid using the name of any SPICE component as the entity name for a VHDL model within the same testbench. This helps prevent naming conflicts and ensures proper functioning of the simulation.
Keeping these considerations in mind will help you effectively utilize SPICE.