How to report duplicated subckts during LVS.
IC Verification & Signoff
How to do the correct setup for identifying duplicate subckts in the design during the LVS run.
In the cases, when you have several references of the same subcircuit in your design, and you want them to be reported during the verification, you can use one of the following statements:
LVS SPICE ALLOW DUPLICATE SUBCIRCUIT NAMES
LVS SPICE OPTION S
Having these statements in your rule file will generate the following warning message:
Warning: Duplicate subckt definition "xxx" at line 80 in file source.spi" previously defined at line 72 in file "source.spi"
The warning will give you information about duplicate subcircuits based on subckt name and pin count (regarding the pin order).
By default, the count of error or warning discrepancy messages issued by the tool is 256 of each type, and the parser will stop reporting warnings after 256 duplicate subcircuits are found.
To increase the limit and control the number of SPICE parsing errors or warning messages that are generated before all further discrepancy messages are suppressed, you can use the following option:
calibre -lvs -cs [message_limit]
You can find more information on this in the
Calibre Verification User's Manual
KB Article ID# KB000111917_EN_US