Tessent The Parameter Default Value for a Verilog

Specifying the parameter default value is mandatory for 1995, 2001, sv31a, and sv2005 formats, and it is not mandatory for the SV2009 format.

Below is the example module with a parameter being used:

module block #(parameter BUS_WIDTH) (
        input [BUS_WIDTH-1:0] bus_data_in,
        output [BUS_WIDTH-1:0] bus_data_out
);
endmodule

If the parameter default value is not specified, then the example error message below is returned:

//  Error: File block.v, Line 10: Syntax error near ( ) ).

To resolve this issue there has to be a specified default value for a parameter or if the format is SV2009 the command below has to be used:

read_verilog block.v -format SV2009