1 | /* |
2 | * rtGetInf.c |
3 | * |
4 | * Code generation for model "BMS". |
5 | * |
6 | * Model version : 1.15 |
7 | * Simulink Coder version : 9.2 (R2019b) 18-Jul-2019 |
8 | * C source code generated on : Thu Aug 20 14:49:14 2020 |
9 | * |
10 | * Target selection: grt.tlc |
11 | * Note: GRT includes extra infrastructure and instrumentation for prototyping |
12 | * Embedded hardware selection: Intel->x86-64 (Windows64) |
13 | * Code generation objectives: Unspecified |
14 | * Validation result: Not run |
15 | */ |
16 | |
17 | /* |
18 | * Abstract: |
19 | * Function to initialize non-finite, Inf |
20 | */ |
21 | #include "rtGetInf.h" |
22 | #define NumBitsPerChar 8U |
23 | |
24 | /* |
25 | * Initialize rtInf needed by the generated code. |
26 | * Inf is initialized as non-signaling. Assumes IEEE. |
27 | */ |
28 | real_T rtGetInf(void) |
29 | { |
30 | size_t bitsPerReal = sizeof(real_T) * (NumBitsPerChar); |
31 | real_T inf = 0.0; |
32 | if (bitsPerReal == 32U) { |
33 | inf = rtGetInfF(); |
34 | } else { |
35 | uint16_T one = 1U; |
36 | enum { |
37 | LittleEndian, |
38 | BigEndian |
39 | } machByteOrder = (*((uint8_T *) &one) == 1U) ? LittleEndian : BigEndian; |
40 | switch (machByteOrder) { |
41 | case LittleEndian: |
42 | { |
43 | union { |
44 | LittleEndianIEEEDouble bitVal; |
45 | real_T fltVal; |
46 | } tmpVal; |
47 | |
48 | tmpVal.bitVal.words.wordH = 0x7FF00000U; |
49 | tmpVal.bitVal.words.wordL = 0x00000000U; |
50 | inf = tmpVal.fltVal; |
51 | break; |
52 | } |
53 | |
54 | case BigEndian: |
55 | { |
56 | union { |
57 | BigEndianIEEEDouble bitVal; |
58 | real_T fltVal; |
59 | } tmpVal; |
60 | |
61 | tmpVal.bitVal.words.wordH = 0x7FF00000U; |
62 | tmpVal.bitVal.words.wordL = 0x00000000U; |
63 | inf = tmpVal.fltVal; |
64 | break; |
65 | } |
66 | } |
67 | } |
68 | |
69 | return inf; |
70 | } |
71 | |
72 | /* |
73 | * Initialize rtInfF needed by the generated code. |
74 | * Inf is initialized as non-signaling. Assumes IEEE. |
75 | */ |
76 | real32_T rtGetInfF(void) |
77 | { |
78 | IEEESingle infF; |
79 | infF.wordL.wordLuint = 0x7F800000U; |
80 | return infF.wordL.wordLreal; |
81 | } |
82 | |
83 | /* |
84 | * Initialize rtMinusInf needed by the generated code. |
85 | * Inf is initialized as non-signaling. Assumes IEEE. |
86 | */ |
87 | real_T rtGetMinusInf(void) |
88 | { |
89 | size_t bitsPerReal = sizeof(real_T) * (NumBitsPerChar); |
90 | real_T minf = 0.0; |
91 | if (bitsPerReal == 32U) { |
92 | minf = rtGetMinusInfF(); |
93 | } else { |
94 | uint16_T one = 1U; |
95 | enum { |
96 | LittleEndian, |
97 | BigEndian |
98 | } machByteOrder = (*((uint8_T *) &one) == 1U) ? LittleEndian : BigEndian; |
99 | switch (machByteOrder) { |
100 | case LittleEndian: |
101 | { |
102 | union { |
103 | LittleEndianIEEEDouble bitVal; |
104 | real_T fltVal; |
105 | } tmpVal; |
106 | |
107 | tmpVal.bitVal.words.wordH = 0xFFF00000U; |
108 | tmpVal.bitVal.words.wordL = 0x00000000U; |
109 | minf = tmpVal.fltVal; |
110 | break; |
111 | } |
112 | |
113 | case BigEndian: |
114 | { |
115 | union { |
116 | BigEndianIEEEDouble bitVal; |
117 | real_T fltVal; |
118 | } tmpVal; |
119 | |
120 | tmpVal.bitVal.words.wordH = 0xFFF00000U; |
121 | tmpVal.bitVal.words.wordL = 0x00000000U; |
122 | minf = tmpVal.fltVal; |
123 | break; |
124 | } |
125 | } |
126 | } |
127 | |
128 | return minf; |
129 | } |
130 | |
131 | /* |
132 | * Initialize rtMinusInfF needed by the generated code. |
133 | * Inf is initialized as non-signaling. Assumes IEEE. |
134 | */ |
135 | real32_T rtGetMinusInfF(void) |
136 | { |
137 | IEEESingle minfF; |
138 | minfF.wordL.wordLuint = 0xFF800000U; |
139 | return minfF.wordL.wordLreal; |
140 | } |
141 |